1. Field of the Invention
This invention relates to a display device, especially to a display device with a DA converter that converts a digital image signal to an analog image signal.
2. Related Art
A liquid crystal display device displays an image by supplying an analog image signal to a pixel element electrode of each pixel element and changing the electric field applied to the liquid crystal for the liquid crystal to align itself. The liquid crystal display device with a DA converter that converts a digital image signal inputted from an outside device into an analog image signal has been widely known. This type of liquid crystal display device will be explained by referring to drawings, hereinafter. FIG. 8 shows a circuit diagram of a conventional active matrix liquid crystal display device. In the pixel element area, the pixel elements GS11, GS12, GS13, - - - are disposed in the first column and the pixel elements GS21, GS22, GS23, - - - are disposed in the second column. That is, a plurality of the pixel elements are arranged in a matrix configuration.
Each pixel element has an N-channel type pixel element selection transistor 72 (thin film transistor). Drain signal lines 61, 62, and 63 extending from a horizontal driver circuit 30 are connected respectively to the drain of the pixel element selection transistor 72. Gate signal lines 51, 52, - - - extending from a vertical driver circuit 40 are connected respectively to the gate of the pixel element selection transistor 72.
The configuration of the pixel element GS11 will be explained by referring to FIG. 9. The source 72s of the pixel element selection transistor 72 is connected to a pixel element electrode 80 of a liquid crystal 21. Also, a storage capacitor 85 for holding the voltage of the pixel element electrode 80 for one field period is disposed. One terminal 86 of the storage capacitor 85 is connected to the source 72s of the pixel element selection transistor 72, and the other terminal 87 is provided with a voltage commonly used among the pixel elements. When a gate scanning signal (H level) is applied to the gate signal line 51, the pixel element selection TFT 72 turns on and an analog image signal is transmitted to the pixel element electrode 80 through the drain signal line 61 and retained in the storage capacitor 85. The image signal voltage applied to the pixel element electrode 80 is then applied to the liquid crystal 21. The liquid crystal aligns itself based on the voltage applied, obtaining a liquid crystal display. The configuration of each of the pixel elements is completely the same as that described above.
The configuration of the horizontal driver circuit 30 will be explained hereinafter. Four-bit portion of the digital image signal D0–D3 are supplied from outside. First latch circuits 1—1, 1-2, 1-3, - - - of four-bit configuration for latching the four-bit portion D0–D3 are disposed for each row. These latch circuits 1—1, 1-2, 1-3, - - - consecutively sample the four-bit portion D0–D3 based on sampling pulses SRP1, SRP2, SRP3, - - - and hold the signals for one horizontal period. The sampling pulse SRP1, SRP2, SRP3, - - - are generated by a shift resistors 10, 10, - - - . That is, the shift resistors 10, 10, - - - generate the sampling pulse, which is a pulse consecutively shifted from a horizontal start signal STH, based on a horizontal clock CKH.
The four-bit portion of the digital signal D0–D3 retained in the first latch circuits 1—1, 1-2, 1-3, - - - is simultaneously latched to second latch circuits 2-1, 2—2, 2-3, - - - of four-bit configuration based on a transfer pulse TP generated upon the end of one horizontal period. Then, the signals are outputted to the drain signal lines 61, 62, 63, - - - after converted into analog image signals through DA converters 3-1, 3-2, 3—3, - - - .
Also, the vertical driver circuit 40 outputs a gate pulse, which is a pulse consecutively shifted from a vertical start signal STV (each pulse is at high-level for one horizontal period), to the gate signal lines 51, 52, - - - based on a vertical clock CKV.
As seen from FIG. 10, a decoding circuit is generally used in the DA converter 3-1. The DA converter 3-1 decodes the four-bit portion D0–D3 by using the decoding circuit 90, selects one reference voltage Vj from the 16 reference voltages V0–V15 supplied to sixteen reference voltage lines, and outputs the selected voltage from an output terminal 91. The decoding circuit 90 is configured from a transistor array, to which the four-bit portion of the digital image signal D0–D3 are supplied. For example, when the digital image signal is (0110), all the four transistors in series 93 are on, selectively outputting the reference voltage V6. The configurations of the DA converters 3-2, 3—3, - - - are the same as the configuration described above.
Next, the operation of the liquid crystal display device with the above configuration will be explained by referring to the timing chart of FIG. 11. Although the first-bit digital image signal D0 is used as an example, the operation is exactly the same as in case of the digital image signal of other bits. The digital image signal D0 changes sequentially to the data D00, D01, D02, - - - with the synchronization with the horizontal clock CKH. Therefore, the data D00 is latched to the latch circuit 1—1 based on the sampling pulse SRP1 and the data D01 is latched to the latch circuit 1—1 based on the sampling pulse SRP2.
The digital image signal D0 is latched to the latch circuits 1—1, 1-2, 1-3, - - - , during one horizontal period. Then the data D00, D01, D02, which have been latched to the latch circuits 1—1, 1-2, 1-3, - - - are then simultaneously latched to the latch circuits 2-1, 2—2, 2-3, - - - . The latch data D00, D01, D02 are converted into analog image signal through the DA converters 3-1, 3-2, 3—3, - - - and outputted to the drain signal lines 61, 62, 63, - - - .
As described above, the DA converters 3-1, 3-2, 3—3, - - - are disposed within the horizontal driver circuit 30 located in a peripheral area of the pixel element in the conventional liquid crystal display device. Therefore, the configuration of the peripheral circuits of the pixel element, especially that of the horizontal driver circuit is complicated, leading to the increased size of the framing area of the liquid crystal panel.
Also, since this type of DA converter uses the decoding circuit 90, the numbers of the transistor terminals and the reference lines increase along with the number of the depth. Therefore, it is very difficult to achieve the liquid crystal display device that can accommodate both integration and multiple-depth display simultaneously.